Field of the Invention
The present invention relates to a display apparatus and a method for driving the same.
Description of the Background Art
Liquid crystal display apparatuses typically include video signal processors that convert video signals input from external devices to desired signal formats. The video signal processors perform various drawing processes and timing adjustments.
The video data signals whose formats have been converted by the video signal processors are transferred to liquid crystal panel driving driver ICs through wire cables for transmitting signals and circuit substrates (such as rigid substrates and flexible substrates).
In recent times, various data formats have been developed and introduced to increase an amount of data transfers per one signal wire. For example, a mini-LVDS mode being one of differential signaling modes is capable of transmitting up to 8 bits of video signals by a pair (a group of two) of signal wires. Such differential signaling mode is not only able to reduce the number of signal wires, but also has a characteristic that the mode is hardly influenced by external noise, thereby being currently used for many liquid crystal display apparatuses.
To increase the amount of data transfers per one signal wire, however, transmission speed of output data needs to be sufficiently faster than that of input data. In an example of the above-mentioned mini-LVDS transmission, transfer speed needs to be three times faster when transmitting 6-bit data and needs to be four times faster when transmitting 8-bit data. If the data transfer speed is increased in this manner, an influence on stray capacitance and wiring inductance on substrate wiring cannot be ignored, thus causing to increase a level of radiation noise. Upon a design of a layout of transmission wiring, wiring needs to be disposed in consideration of the characteristics (such as parasitic capacitance). Moreover, for example, a noise countermeasure component needs to be installed as necessary, thereby simply causing an increase in cost and an area of a substrate.
To solve the problems, measures to divide transfer data between a video signal processor and a driver IC by an odd number and an even number to reduce transfer speed of the output data by half and a method for reducing transfer speed using a plurality of line memories (see Japanese Patent Application Laid-Open No. 10-207434 (1998), for example) have been taken into consideration.
A method for reading data temporarily stored in a memory at a frequency of each RGB (see Japanese Patent Application Laid-Open No. 2009-151243) is also considered.
In the mode that divides the output data by the even number and the odd number for the transfer, the number of data wires doubles, and thus a region of wires in a circuit substrate doubles. This results in an increased area of the substrate. Furthermore, a problem arises that power consumption used for data signals doubles. Moreover, the mode is only applicable to a driver IC compatible with the same mode, so that the use of the mode causes constraints of components.
The conventional mode using the line memories (or parallel driving that divides output into two) waits for completion of data writing of one horizontal period and performs data reading. In this case, the line memories of at least two horizontal periods are needed to avoid overwriting of data stored in a memory. Thus, when a SRAM is built in a video signal processing integrated circuit for cost reduction, the SRAM takes up an increased area of a chip.
Then, a method for reducing transfer speed of output by half (dividing output into two) is known, but the number of data clocks during a data blank period is also reduced by half, thereby possibly resulting in insufficient constraints of timing determined by a driver IC at a subsequent stage depending on a usage state. To solve the problem, a demand for the data blank period to input equipment needs to be expanded, and existing equipment may not be possibly used in some cases.